1. Field of the Invention
The present invention relates to a stack control system. More particularly, the invention concerns a stack control system in which information issued from an information source is transferred to an information receiving unit by way of a stack unit which has a plurality of temporal stores referred to as the store stack.
2. Description of the Prior Art
In order to have a better understanding of the invention, description will first be made of a hitherto known stack control system in some detail by referring to FIGS. 1 and 2 of the accompanying drawings. In FIG. 1, a store request issued from a store request circuit 111 contained in a processing unit 11 as an information generating source is stored temporarily in a stack unit 12 before the information is stored in a memory unit 13. It is assumed that the stack unit 12 incorporates therein two store stacks 121 (A and B). When the store request signal REQ issued from the store request circuit 111 is supplied to the stack unit 12, the output signal from an AND circuit 124 is checked to detect whether both of STACK-A BUSY signal produced from a stack-A busy latch 122 and STACK-B BUSY signal from a stack-B busy latch 123 are logic "1's" or not. If the AND product is found not to be logic "1", meaning that either the stack-A or stack-B is not busy (i.e. not in use), the output from an AND circuit 125 will be logic "1". Then, an accept signal ACPT is issued from a latch 126, whereby the concerned information such as data, address, control signal and the like is stored in the store stack which is idle at that time. In response to the accept signal ACPT, the request signal REQ is reset by the store request circuit 111 of the processing unit 11. The store request circuit 111 is now in the state to prepare for issuance of a next store request. When the information stored in one of the store stacks 121 (A and B) is transferred to the memory unit 13, the corresponding STACK BUSY signal is reset, indicating that the associated store stack is now idle.
FIG. 2 shows a time chart to illustrate store stack operations of the system shown in FIG. 1 as a function of time. In the initial state, both the stacks 121-A and 121-B are idle. As can be seen from this diagram, the first accept signal ACPT 1 is issued in response to the first store request signal REQ 1 . The signal STACK-A BUSY becomes then logic "1", while the stack store request signal REQ 1 is reset. For the second store request REQ 2 , the signal STACK-B BUSY also takes logic "1" level in a similar manner. However, for the third request signal REQ 3 , the accept signal ACPT is not issued instantly. When the signal STACK-A BUSY is reset, that is, when the store request REQ stored in the stack A is accepted by the memory unit 13 to make the stacking of information unnecessary, the accept signal ACPT becomes logic "1".
In connection with the issuance rate of the store request signal produced from the processing unit 11, it will be seen that the rate at which the signals are transmitted reciprocatively among the units 11, 12 and 13 is subjected to a limitation, making it essentially impossible to further increase the rate of the store request signal in the case of the hitherto known stack control system, because any succeeding request signal REQ is inhibited from being issued until the accept signal ACPT is restored. As a consequence, the function of the stack unit 12 which is inherently destined to accommodate any difference in the operation speed between the processing unit 11 and the memory unit 13 can not be fully made use of.